module RF(iClk, iRegWrite, iReset, iReadReg1, iReadReg2, iWriteReg, iWriteData, oReadData1, oReadData2);
	input iClk, iRegWrite, iReset;
	input [4:0] iReadReg1, iReadReg2, iWriteReg;
	input [31:0] iWriteData;
	output [31:0] oReadData1, oReadData2;

	reg [31:0] oReadData1, oReadData2;

	reg [31:0] Cells[31:1];

	always @(posedge iClk or posedge iReset)
	begin
		if(iReset)//reset
		begin
Cells[1] <= 32'b0;
Cells[2] <= 32'b0;
Cells[3] <= 32'b0;
Cells[4] <= 32'b0;
Cells[5] <= 32'b0;
Cells[6] <= 32'b0;
Cells[7] <= 32'b0;
Cells[8] <= 32'b0;
Cells[9] <= 32'b0;
Cells[10] <= 32'b0;
Cells[11] <= 32'b0;
Cells[12] <= 32'b0;
Cells[13] <= 32'b0;
Cells[14] <= 32'b0;
Cells[15] <= 32'b0;
Cells[16] <= 32'b0;
Cells[17] <= 32'b0;
Cells[18] <= 32'b0;
Cells[19] <= 32'b0;
Cells[20] <= 32'b0;
Cells[21] <= 32'b0;
Cells[22] <= 32'b0;
Cells[23] <= 32'b0;
Cells[24] <= 32'b0;
Cells[25] <= 32'b0;
Cells[26] <= 32'b0;
Cells[27] <= 32'b0;
Cells[28] <= 32'b0;
Cells[29] <= 32'b0;
Cells[30] <= 32'b0;
Cells[31] <= 32'b0;
end
		else if(iRegWrite && iWriteReg!=5'b0)//register write, but not on $0
			Cells[iWriteReg] <= iWriteData;
	end

	always @(*) //asynchronous read
	begin
		if(iReadReg1==5'b0)
			oReadData1 = 31'b0; //hardwired 0
		else
			oReadData1 = Cells[iReadReg1];
	end
	
	always @(*)
	begin
		if(iReadReg2==5'b0)
			oReadData2 = 31'b0;
		else
			oReadData2 = Cells[iReadReg2];
	end
endmodule